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BSI
FEATURES
Very Low Power/Voltage CMOS SRAM 1M x 16 or 2M x 8 bit switchable
DESCRIPTION
BS616LV1626
* Vcc operation voltage : 4.5 ~ 5.5V * Very low power consumption : Vcc = 5.0V C-grade: 113mA (@55ns) operating current I -grade: 115mA (@55ns) operating current C-grade: 90mA (@70ns) operating current I -grade: 92mA (@70ns) operating current 15uA (Typ.) CMOS standby current * High speed access time : -55 55ns -70 70ns * Automatic power down when chip is deselected * Three state outputs and TTL compatible * Fully static operation * Data retention supply voltage as low as 1.5V * Easy expansion with CE1, CE2 and OE options * I/O Configuration x8/x16 selectable by CIO, LB and UB pin
The BS616LV1626 is a high performance, very low power CMOS Static Random Access Memory organized as 1,048,676 words by 16 bits or 2,097,152 bytes by 8 bits selectable by CIO pin and operates in a Vcc range of 4.5V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 15uA at 5.0V/25oC and maximum access time of 55ns at 5.0V/85oC . This device provide three control inputs and three states output drivers for easy memory expansion. The BS616LV1626 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS616LV1626 is available in 48-pin 12mmx20mm TSOP1 package.
PRODUCT FAMILY
PRODUCT FAMILY OPERATING TEMPERATURE +0 O C to +70 O C -40 O C to +85 O C Vcc RANGE 4.5V ~ 5.5V 4.5V ~ 5.5V SPEED (ns)
55ns : 4.5~5.5V 70ns : 4.5~5.5V
POWER DISSIPATION STANDBY Operating
(ICCSB1, Max) (ICC, Max)
PKG TYPE
Vcc=5V
Vcc=5V
55ns
Vcc=5V
70ns
BS616LV1626TC BS616LV1626TI
55 / 70 55 / 70
110 uA 220 uA
113mA 115mA
90mA 92mA
TSOP1-48(12mmx20mm) TSOP1-48(12mmx20mm)
PIN CONFIGURATIONS
A4 A3 A2 A1 A0 /CE1 D0 D1 D2 D3 Vcc CIO Vss D4 D5 D6 D7 A19 /WE A18 A17 A16 A15 A14 1 48 47 46 A5 A6 A7 /OE /UB /LB CE2 SAE D15 D14 D13 D12 Vss Vcc D11 D10 D9 D8 A8 A9 A10 A11 A12 A13
BLOCK DIAGRAM
A19 A15 A14 A13 A12 A11 A10 A9 A8 A17 A7 A6 Address Input Buffer 24 Row Decoder 4096 Memory Array 4096 x 4096
9 10
13
BS616LV1626TC BS616LV1626T I
37
4096 D0 16(8) Data Input Buffer 16(8) Column I/O
16 17
. . . .
D15 CE1 CE2 WE OE UB
. . . .
Write Driver
16(8) Sense Amp 256(512) Column Decoder
16(8) Data Output
Buffer
27 24 25
16(18) Control Address Input Buffer
48-pin 12mmx20mm TSOP1 top view
LB CIO Vdd Vss
A16 A0 A1 A2 A3 A4 A5 A18 (SAE)
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
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BSI
PIN DESCRIPTIONS
BS616LV1626
Name
A0-A19 Address Input SAE Address Input CIO x8/x16 select input
Function
These 20 address inputs select one of the 1,048,576 x 16-bit words in the RAM. This address input incorporates with the above 20 address inputs select one of the 2,097,152 x 8-bit bytes in the RAM if the CIO is LOW. Don't use when CIO is HIGH. This input selects the organization of the SRAM. 1,048,576 x 16-bit words configuration is selected if CIO is HIGH. 2,097,152 x 8-bit bytes configuration is selected if CIO is LOW. CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when data read from or write to the device. If either chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected. The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive. Lower byte and upper byte data input/output control pins. The chip is deselected when both LB and UB pins are HIGH. These 16 bi-directional ports are used to read data from or write data into the RAM. Power Supply Ground
CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input
WE Write Enable Input
OE Output Enable Input
LB and UB Data Byte Control Input D0 - D15 Data Input/Output Ports Vcc Gnd
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BSI
TRUTH TABLE
MODE CE1 H Fully Standby X Output Disable L L H H H X CE2 X X X X X X L Read from SRAM ( WORD mode ) L H L H H H L L Write to SRAM ( WORD mode ) L H X L H H L Read from SRAM ( BYTE Mode ) Write to SRAM ( BYTE Mode ) L H L H L X X X H L L H L L X A-1 X X X OE WE CIO LB X UB X X SAE
BS616LV1626
D0~7
D8~15
VCC Current
High-Z
High-Z
ICCSB, ICCSB1
High-Z Dout High-Z Dout Din X Din Dout
High-Z High-Z Dout Dout X Din Din High-Z
ICC
ICC
ICC
ICC
L
H
X
L
L
X
X
A-1
Din
X
ICC
ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL VTERM TBIAS TSTG PT IOUT PARAMETER
Terminal Voltage Respect to GND with
OPERATING RANGE
UNITS
V
O O
RATING
-0.5 to Vcc+0.5 -40 to +85 -60 to +150 1.0 20
RANGE
Commercial Industrial
AMBIENT TEMPERATURE
0 C to +70 C -40 C to +85 C
O O O O
Vcc
4.5V ~ 5.5V 4.5V ~ 5.5V
Temperature Under Bias Storage Temperature Power Dissipation DC Output Current
C C
W mA
CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
SYMBOL
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CIN CDQ
PARAMETER Input Capacitance Input/Output Capacitance
CONDITIONS
MAX.
UNIT
VIN=0V VI/O=0V
10 12
pF pF
1. This parameter is guaranteed and not 100% tested.
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DC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC )
PARAMETER NAME
VIL VIH IIL ILO VOL VOH ICC
(4)
BS616LV1626
TEST CONDITIONS
Vcc=5V Vcc=5V
PARAMETER
Guaranteed Input Low Voltage(3) Guaranteed Input High Voltage(3) Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Power Supply Current Standby Current-TTL
MIN. TYP.
-0.5 --
(1)
MAX.
0.8 Vcc+0.3 1 1 0.4 -115 92 2.5
UNITS
V V uA uA V V mA mA
2.2 ---2.4 ----
---------
Vcc = Max, VIN = 0V to Vcc Vcc = Max, CE1 = VIH , or CE2 = ViL, or OE = VIH, VI/O = 0V to Vcc Vcc = Max, IOL= 2mA Vcc = Min, IOH= -1mA CE1 = VIL and CE2 = VIH , IDQ = 0mA, F = Fmax(2) CE1 = VIH or CE2 = VIL , IDQ = 0mA CE1 Vcc-0.2V, or CE20.2V, VINVcc - 0.2V or VIN 0.2V
55ns 70ns Vcc=5V Vcc=5V Vcc=5V
ICCSB
(5)
Vcc=5V
ICCSB1
Standby Current-CMOS
Vcc=5V
--
15
220
uA
1. Typical characteristics are at TA = 25oC. 2. Fmax = 1/tRC . 3. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 4. Icc_Max. is 113mA(@55ns) / 90mA(@70ns) during 0~70oC operation. 5. IccsB1 is 110uA at Vcc=5.0V and TA=70oC.
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DATA RETENTION CHARACTERISTICS ( TA = -40oC to +85oC )
SYMBOL
VDR
BS616LV1626
TEST CONDITIONS
CE1 Vcc - 0.2V or CE2 0.2V or LB Vcc - 0.2V and UB Vcc - 0.2V VIN Vcc - 0.2V or VIN 0.2V CE1 Vcc - 0.2V or CE2 0.2V or LB Vcc - 0.2V and UB Vcc - 0.2V VIN Vcc - 0.2V or VIN 0.2V
PARAMETER
Vcc for Data Retention
MIN.
1.5
TYP. (1)
--
MAX.
--
UNITS
V
(3)
ICCDR
Data Retention Current Chip Deselect to Data Retention Time
--
1.5
5
uA
tCDR tR
0 See Retention Waveform TRC
(2)
---
---
ns ns
Operation Recovery Time
1. Vcc = 1.5V, TA = + 25OC 2. tRC = Read Cycle Time 3. IccDR(Max.) is 2.5uA at TA=70OC.
LOW VCC DATA RETENTION WAVEFORM (1) ( CE1 Controlled )
Data Retention Mode
Vcc
VIH
Vcc
VDR 1.5V
Vcc
t CDR
CE1 Vcc - 0.2V
tR
VIH
CE1
LOW VCC DATA RETENTION WAVEFORM (2) ( CE2 Controlled )
Data Retention Mode
Vcc
Vcc
VDR 1.5V
Vcc
t CDR
tR
CE2 0.2V
CE2
VIL
VIL
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BSI
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
BS616LV1626
KEY TO SWITCHING WAVEFORMS
Vcc / 0V 1V/ns 0.5Vcc CL = 30pF+1TTL CL = 100pF+1TTL
WAVEFORM INPUTS MUST BE STEADY MAY CHANGE FROM H TO L MAY CHANGE FROM L TO H DON T CARE: ANY CHANGE PERMITTED DOES NOT APPLY OUTPUTS MUST BE STEADY WILL BE CHANGE FROM H TO L WILL BE CHANGE FROM L TO H CHANGE : STATE UNKNOWN CENTER LINE IS HIGH IMPEDANCE "OFF "STATE
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load
,
AC ELECTRICAL CHARACTERISTICS ( TA = -40oC to +85oC )
READ CYCLE JEDEC PARAMETER PARAMETER NAME NAME
CYCLE TIME : 70ns CYCLE TIME : 55ns MIN. TYP. MAX.
Vcc = 4.5~5.5V
DESCRIPTION
Read Cycle Time Address Access Time Chip Select Access Time Chip Select Access Time Data Byte Control Access Time Output Enable to Output Valid Chip Select to Output Low Z (CE2,CE1) (LB,UB) (CE1) (CE2) (LB,UB)
MIN. TYP. MAX.
Vcc = 4.5~5.5V
UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns
tAVAX tAVQV tELQV tELQV tBA tGLQV tELQX tBE tGLQX tEHQZ tBDO tGHQZ tAXOX
tRC tAA t ACS1 t ACS2 tBA (1) tOE tCLZ tBE tOLZ tCHZ tBDO tOHZ tOH
70 -----10 5 5 ---10
--------------
-70 70 70 35 35 ---35 35 30 --
55 -----10 5 5 ---10
--------------
-55 55 55 30 30 ---30 30 25 --
Data Byte Control to Output Low Z Output Enable to Output in Low Z
Chip Deselect to Output in High Z (CE2,CE1) Data Byte Control to Output High Z (LB,UB) Output Disable to Output in High Z Data Hold from Address Change
NOTE : 1. tBA is 35ns/30ns (@speed=70ns/55ns) with address toggle . tBA is 70ns/55ns (@speed=70ns/55ns) without address toggle .
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BSI
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
ADDRESS
BS616LV1626
t RC t AA t OH
t OH
D OUT
READ CYCLE2 (1,3,4)
CE2
t t
ACS2
ACS1
CE1
t
D OUT
(5) CLZ
(5) t CHZ
READ CYCLE3 (1,4)
ADDRESS
t RC
t
OE
AA
t
CE2
OE
t
OH
t t t t
(5) CLZ
ACS2
CE1
OLZ
ACS1
t t
OHZ CHZ
(5)
(1,5)
LB,UB
t
BE
t t
BA
BDO
D OUT
NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE1 = VIL and CE2 = VIH. 3. Address valid prior to or coincident with CE1 transition low and CE2 transition high. 4. OE = VIL . 5. The parameter is guaranteed but not 100% tested.
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BSI
AC ELECTRICAL CHARACTERISTICS ( TA =
WRITE CYCLE JEDEC PARAMETER PARAMETER NAME NAME -40oC to +85oC ) DESCRIPTION
Write Cycle Time Chip Select to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write recovery Time MIN. TYP. MAX.
Vcc = 4.5~5.5V
BS616LV1626
CYCLE TIME : 70ns CYCLE TIME : 55ns
Vcc = 4.5~5.5V
MIN. TYP. MAX.
UNIT ns ns ns ns ns ns ns ns ns ns ns ns
t AVAX t E1LWH t AVWL t AVWH t WLWH t WHAX t BW t WLQZ t DVWH t WHDX t GHQZ t WHOX
t WC t CW t AS t AW t WP t WR t BW(1) t WHZ t DW t DH t OHZ t OW
70 70 0 70 35 (CE2,CE1,WE) 0 30 -30 0 -5
-------------
-------30 --30 --
55 55 0 55 30 0 25 -25 0 -5
-------------
-------25 --25 --
Date Byte Control to End of Write (LB,UB) Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Disable to Output in High Z End of Write to Output Active
NOTE : 1. tBW is 30ns/25ns (@speed=70ns/55ns) with address toggle. ; tBW is 70ns/55ns (@speed=70ns/55ns) without address toggle.
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1)
ADDRESS
t
WC
t WR
OE
(3)
CE2
(5)
t CW
CE1
(5)
(11)
t
LB,UB
(5)
BW
t AW
WE
(3)
t AS
(4,10)
t WP
(2)
t OHZ
D OUT
t DH t DW
D IN R0201-BS616LV1626
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BSI
WRITE CYCLE2 (1,6)
BS616LV1626
t WC
ADDRESS
CE2
(11)
CE1
(5)
t t
CW
BW
LB,UB
(5)
t
WE
AW
t WP
t WR
(3)
(2)
t AS
(4,10)
t WHZ
D OUT
t t DW t
OW
(7)
(8)
DH
(8,9)
D IN
NOTES:
1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE2, CE1 and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE2 going low, or CE1 or WE going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE2 high transition or CE1 low transition or LB,UB low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL ). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE2 is high or CE1 is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE2 going high or CE1 going low to the end of write.
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BSI
ORDERING INFORMATION
BS616LV1626
Z YY
SPEED 55: 55ns 70: 70ns PKG MATERIAL -: Normal G: Green P: Pb free GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC
BS616LV1626 X X
PACKAGE T : TSOP1-48(12mmx20mm)
Note: BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support systems and critical medical instruments.
PACKAGE DIMENSIONS
TSOP1-48 (12mm x 20mm)
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Revision 2.1 Jan. 2004

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